xPU Accelerator Offload Functions

As covered in our first xPU webcast “SmartNICs and xPUs: Why is the Use of Accelerators Accelerating,” we discussed the trend to deploy dedicated accelerator chips to assist or offload the main CPU. These new accelerators (xPUs) have multiple names such as SmartNIC, DPU, IPU, APU, NAPU. If you missed the presentation, I encourage you to check it out in the SNIA Educational Library where you can watch it on-demand and access the presentation slides.

This second webcast in this SNIA Networking Storage Forum xPU webcast series is “xPU Accelerator Offload Functions” where our SNIA experts will take a deeper dive into the accelerator offload functions of the xPU. We’ll discuss what problems the xPUs are coming to solve, where in the system they live, and the functions they implement, focusing on:

  • Network Offloads 
    • Virtual switching and NPU
    • P4 pipelines
    • QoS and policy enforcement
    • NIC functions
    • Gateway functions (tunnel termination, load balancing, etc)
  • Security Offloads
    • Encryption
    • Policy enforcement
    • Key management and crypto
    • Regular expression matching
    • Firewall
    • Deep Packet Inspection (DPI)
  • Compute Offloads
    • AI calculations, model resolution
    • General purpose processing (via local cores)
    • Emerging use of P4 for general purpose
  • Storage Offloads
    • Compression and data at rest encryption
    • NVMe-oF offload
    • Regular expression matching
    • Storage stack offloads

This webcast will be live on June 29, 2022 at 11:00 am PT/2:00 pm ET. I encourage you to register today and bring your questions for our experts. We look forward to seeing you.

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